The Non Maskable Interrupt

I would like to take some time to discuss a wonderful coding tool that is provided by a number of modern chips makers. I am (of course) talking about the Non Maskable Interrupt (NMI).

In general, there are two System Registers that are used to manage system interrupts – the Interrupt Mask Register and the Interrupt Cause Register. The Interrupt Mask Register allows the root user to disable/enable specific interrupts. This register contains a bit for each interrupt type. The Interrupt Cause Register indicates when the interrupts are ready for service. This register also contains a bit for each interrupt type.

So when an interrupt comes into the system, the appropriate bit is set in the Interrupt Cause Register. If the appropriate bit is set in the Interrupt Mask Register, then the interrupt is generated and serviced by the appropriate Exception Handler. Otherwise, the system is not interrupted and the interrupt is essentially ignored.

Non Maskable Interrupt Defined

By definition, the Non Maskable Interrupt is an interrupt that cannot be disabled. An NMI is periodically (and regularly) generated by the CPU. This functionality provides two benefits:

The first benefit is to detect a hung or wedged system. That is, a system that does not seem to be doing anything. This is often times the result of a very tight coding loop. In this case, a counter is added to the system scheduler. This counter is incremented every time the scheduler completes its main processing loop. If this counter does not get incremented over long periods of time, then the system is hung in some specific task and normal system processing has been suspended. The NMI Exception Handler can easily detect this and generate a panic. Additional counters and flags can then be added through out the system to ensure that system processing is proceeding in a healthy fashion. The NMI Exception Handler then can periodically check these counters and flags and thus detect when system processing is in an abnormal state.

Measuring System Performance & Code Coverage

The second benefit is to help measure system performance and code coverage. The Non Maskable Interrupt Exception Handler uses a Code Array to achieve this purpose. The kernel code space is divided into buckets, where each bucket is an entry in the Code Array. The size of a bucket is configurable. Each bucket is used to keep track of code hits. Thus each bucket keeps track of the number of times a section of code has been entered. Thus for a a bucket size of B, let PC be the program counter when an NMI occurs. Then the specific bucket is identified by (PC / B).

So to measure system performance and code coverage for a given test:

1) Clear the Code Array.

2) Run the test.

3) Examine the Code Array.

If we order the buckets by the number of items descending, then we have a clear indication of the code priority and usage during the test. This can be used to detect anomalies and to shine a spot light on the code.

So go forth and make use of this wonderful tool.